With the advance of semiconductor technology, the emergence of deep sub-micron or nanometer technologies allows analog designers to design with ever faster transistors, thereby enabling the implementation of high-speed circuitries and systems. In the case of a CTSD modulator, the finer geometry (such as 65 nm) transistors allow for multi-GHz sampling clock frequency. Because of this, the input signal bandwidth that the ADC can handle is also boosted dramatically, which may introduce additional sensitivity to clock skews.
FIG. 1 is a CTSD modulator 10 which includes an input terminal 12, a summation block 14, a loop filter 16, a flash analog-to-digital converter (flash) 18, an optional delay locked-loop (DLL) 20, a digital-to-analog converter (DAC) 22, and an output terminal 24, where the summation block 14 may be part of the loop filter 16. The input terminal 12 receives an analog signal that the CTSD modulator 10 converts into a digital signal at the output terminal 24. Referring to FIG. 1, the modulator ADC 10 includes a forward signal path from the input terminal 12 to output terminal 24, including serially connected the summation block 14, loop filter 16, and ADC 18, and a feedback signal path from the output terminal 24 to the input terminal 12, including the DAC 22. DLL 20 receives a clock signal and outputs aligned clocks to the ADC 18 and DAC 22 to drive both blocks. The summation block 14 is configured as a subtractor that subtracts the output of DAC 22 from the input signal to generate a residual signal that is fed to an input of loop filter 16. The loop filter 16 may be a low-pass filter or bandpass filter for smoothing the residual signal which ADC 18 may convert into a digital output at output terminal 24. The digital output is fed into an input of DAC 22 which converts the digital output into analog form to be compared with the input signal.
The two major circuit blocks, ADC 18 and DAC 22, are driven by clocks generated from DLL 20. During operation, the clocks fed into ADC 18 and DAC 22 may include timing differences. For example, referring to FIG. 1, ADC 18 may perform signal sampling at time instant 26, or the rising edge of a first clock cycle, while the DAC 22 may perform digital-to-analog conversion over time period 28 which starts at the rising edge of a second clock cycle that follows the first clock cycle. Ideally, the time instant 26 and the outset of the time period 28 should happen at the same time. However, in practice, a time difference between these two may exist, which may introduce phase shifts in the frequency domain. The phase shift may be detrimental to the stability of high-order loop filters 16 contained in the feedback path.
Therefore, before the CTSD modulator is shipped to a customer, the clock skew between these two major blocks may be tuned to correct or compensate for the high order effects. The clock to the ADC 18 may be either delayed or advanced to match the clock to DAC 22. Delaying the clock to ADC 18 flattens the noise transfer function (NTF) of the CTSD modulator 10, while advancing the clock would reduce the meta-stability of ADC 18. Therefore, it is desirable that the timing difference between ACD 18 and DAC 22 can be fine-tuned to the degree of a few percentage of the clock period. For example, for certain applications, the delay needs to be below 5 ps which is finer or shorter than a simple inverter can achieve. For faster CTSD converters, the capability of sub-gate delay adjustment is very important.
Current art uses phase interpolation to generate sub-gate delays. FIG. 2 illustrates a DLL that uses phase interpolation to generate sub-gate delay. The DLL 30 includes a delay line 32 which includes a phase interpolator 34, a phase lock element 42 that includes a phase frequency detector 36, a charge pump 38, and a loop filter 40, a DAC pulse driver 44, and a flash clock driver 46. Additionally, DLL 30 includes a plurality of multiplexers 48, 50. To overcome sub-gate delay variations caused by manufacturing, supplying voltage, and operating temperature variation (PVT), closed loop (DLL) is commonly used. Referring to FIG. 2, a source clock is supplied to the delay line 32 in which the phase interpolation circuit 34 may generate delays between two clock outputs. The closed loop locks the input clock and the output of the dummy multiplexer 50. In practice, since DAC 22 requires a clean clock that has little jitters, the first clock output passes through a dummy multiplexer 50 and is supplied to the phase lock element 42 at which the first clock output is phase locked with the source clock before supplied to the DAC pulse driver 44. In the phase lock element 42, the phase frequency detector 36 detects phase and frequency difference between the source clock and the output of the dummy multiplexer 50. The charge pump 38 converts the phase difference into a voltage signal that is low-pass filtered by the loop filter 40. The output from the loop filter 40 is the control voltage that is fed back into the delay line 32 including delay elements. DAC driver 44 supplies a clock signal to the DAC 22. The second clock output from the delay line 32 include multiple delay lines generated by phase interpolator 34. These delay lines are supplied to multiplexer 48 that is controlled by a digital input. By adjusting the digital input, the second clock output with a different amount of phase delay is supplied to flash ADC clock driver 46 which drives the ADC 18.
In order to tap out the different phase delays generated by the phase interpolator 34, many levels of multiplexers are needed. The wider the adjustable range and the finer the timing resolution are, the more multiplexers are needed. However, multiplexers need to be matched to each other. Therefore, multiple multiplexers in CTSD modulators increase the difficulties of circuit design.
Another challenge for nanometer circuitry is low voltage supply, which may be as low as 1V for certain designs.